1. Field of Use
This invention relates to a multiprocessor computing system featuring global data multiplation.
2. Prior Art
A multiprocessor computing system comprises a plurality of independently or semi independently operating intelligent units or processors which are generally interconnected to a communications bus for communication. The system may also include other units which are passive; that is, units operated only under the direction and control of an intelligent unit. An example of a passive unit is a main working memory connected to the communication bus and shared by the intelligent units.
The objective of distributing the system intelligence among a plurality of processors which may be functionally the same or different, such as a central processor or an I/O processor, is to improve the processing throughput of the system by having different processes and tasks concurrently performed by the various units. Several multiprocessor computing systems are known to have architectures which span from loosely coupled architectures. The extreme of these is a set of independent processors which may exchange some information through a bus to tightly coupled architectures, which at the extreme is a set of processors which share a plurality of resources such as memories, registers, input/output units and are conditioned by each other for operation.
Both types of architectures have advantages and trade-offs which may be summarized as follows. Loosely coupled architectures feature high performance of each individual processor but do not provide for ease of real-time load balancing among processors. Tightly coupled architectures feature by contrast, ease of load balancing and distribution among processors but suffer from the bottleneck produced by the sharing of common resources through one or more buses, also a common resource.
An intermediate approach is one having common resources and local resources such as local memories in each processor. The common resources are accessible to all the processors through the system bus and the local resources being accessible to the pertaining processor. Cache memories, may be viewed in this perspective as local memories.
In this arrangement, contention among processors in accessing common resources may be reduced because most of the information on which they must work may be stored and handled by the local resources. However, in order to make the work results available to the other processors, a copy of the work done must be available in the common resources. This again involves some occupation of the system bus for both writing and reading the requested information and processors activity for performing such operations. The trade-off is further increased by the need to assure congruence among information stored in local resources and the copy of information which is stored in the common working memory.
To overcome these trade-offs, it is strictly mandatory that any information of interest to any of the processors always be stored in common resources and not duplicated in the local resources. The only exception to this requirement may be considered for unmodifiable information, such as operating system instructions which do not contain variable parameters and addresses. They are read only information and can be duplicated at will in any of the local memories.
A proposed alternative approach leads to the concept of shared global resources and is exemplified by European patent application published with number which corresponds to U.S. Pat. No. 4,713,834.
In summary, each processor in a multiprocessor system may have its own local resources, namely a local memory which needs not to be accessed through the system bus. However, the same local resources may be viewed as distributed common resources, accessible by any processor in the system through the system bus. Clearly, this architecture provides some advantage free from the above mentioned restrictions. However, in order to provide increased performance, it still requires that most, if not all, of the information required by more than one processor be stored in a common non-local resource which still must be accessed through the system bus. Thus, the bottleneck resulting from the system bus and common memory sharing is still present eve though lessened to some extent.